Until now, integrated circuits (IC) have been increased in an integration density and performance by miniaturization of transistors, that is, scaling thereof.
As one method for improving in scaling further, recently, a transistor designed to have a junctionless (JL) structure has been considered. In this junctionless MISFET (metal-insulator-semiconductor field effect transistor), the source/drain region and the channel region are of the same impurity conductivity type, and there is no junction between the source/drain region and the channel region. Thus, a FET having such a structure is called a junctionless FET.
In the junctionless FET, the impurity concentration profiles of the source/drain region and the channel region need not be finely controlled. Thus, the junctionless FET has the advantages that its manufacturing process is very simple and it can be miniaturized without being limited to formation of a source/drain junction.
Since, however, the source/drain region and the channel region are of the same conductivity type in the junctionless FET, a depletion layer is formed in a channel region immediately below a gate electrode when a transistor is driven; thus, the transistor is turned off. In order to generate a large on-state current in the transistor, the junctionless FET is set at a relatively high impurity concentration to have a channel concentration of about 1019 cm−3.
It is thus desirable that the channel width of the junctionless FET be set to a relatively narrow width of about 10 nm and moreover a multigate structure for controlling a channel by the gate electrode from multiple directions be applied to a FET to form a junctionless FET having a structure in which a depletion layer extends from multiple directions in the channel region. Accordingly, in the junctionless FET, the on/off state of a channel in the channel region is controlled by adjusting the width of the depletion layer in the channel region.
Since the source/drain region and the channel region are of the same carrier conductivity type (conductivity type impurities), the junctionless FET is basically driven in normally-on operation. Therefore, it is one technical object to attain a junctionless FET that is driven in normally-off operation.
As one method for forming a junctionless FET in normally-off operation, there is a method for varying the material of a gate electrode from an n-type junctionless FET to a p-type junctionless FET and adjusting the work function of the gate electrode of each of the FETs. Thus, the fact that a normally-off operation can be performed in each of the n-type and p-type junctionless FETs is verified in n-type and p-type junctionless FETs that are formed using monocrystalline silicon. However, when the work function of the material of the gate electrode is controlled for each of the n-type and p-type junctionless FETs, a process for forming the gate electrode becomes complicated. Accordingly, it is likely that an IC including transistors will be manufactured at high cost. It is thus desirable that both the n-type and p-type junctionless FETs be caused to perform a normally-off operation using gate electrodes of the same material in both the n-type and p-type junctionless FETs.
Furthermore, recently, the miniaturization of devices is approaching its physical limit, and it has been considered for not only the devices to be miniaturized but also ICs to be stacked three-dimensionally as a means for increasing the performance and integration density of the devices and circuits.
As a method for stacking ICs (semiconductor chips), a method for stacking IC chips which are manufactured separately and then connecting the stacked chips by TSV (through silicon via), micro-bumps or the like and a method for stacking semiconductor regions (active regions and channel materials of an FET) in which devices are formed, on an interlayer insulating film on the substrate, are considered.
In a 3D-IC manufactured by the method for stacking channel materials on an interlayer insulating film, devices and circuits can be formed in a semiconductor region on the interlayer insulating film by a normal CMOS process; thus, high IC integration density and low chip cost can easily be achieved.
Furthermore, monocrystalline channel materials can be formed on an interlayer insulating film by a bonding method or the like. However, in order to decrease manufacturing costs, it is desirable to use a technique of depositing channel materials (semiconductor regions) on an insulating film by sputtering or the like and making the deposited channel materials polycrystalline. It is reported that polycrystalline silicon and polycrystalline germanium have been used as channel materials for a FET.
Germanium is taken into consideration as a channel material of the next-generation MISFET because its carrier mobility is higher than that of silicon. If a Si layer is interposed between a channel region made of polycrystalline germanium and a high dielectric film, interface characteristics between the channel region and the high dielectric film are improved, and carrier mobility is increased. However, there are no findings about any advantage brought about by the fact that a Si layer is formed in an interface between a gate insulating film and polycrystalline germanium.